1. Field of the Invention
This invention relates generally to advanced CMOS technology and more particularly, it relates to a method for fabricating advanced CMOS integrated circuits so as to prevent boron penetration through thin gate oxide of P-channel devices.
2. Description of the Prior Art
As is generally well-known in the art of CMOS technology, a CMOS (complementary metal-oxide semiconductor) device is formed of an N-channel MOS device and a P-channel MOS device. In order to increase the speed of the CMOS devices, there has existed in the micro-electronics industry over the last two decades an aggressive scaling-down of the channel length dimensions. However, as the channel length reduction occurs, the gate oxide thickness has to be likewise reduced down so as to avoid short channel effects.
Thus, there has been proposed heretofore of using a p.sup.+ -type polycrystalline silicon (poly-Si) gate so as to provide a surface channel feature in P-channel MOS devices in advanced CMOS structures. This is due to the fact that it is known that surface-channel P-channel MOS devices with p.sup.+ -type poly-Si gates can improve short-channel and sub-threshold I-V characteristics and produce better controllability of the threshold voltage. Typically, BF.sub.2.sup.+ ions are implanted simultaneously with the forming of the p.sup.+ poly-Si gate and a p.sup.+ -n shallow junction. The presence of fluorine ions during the BF.sub.2 implantation enhances the diffusion of boron ions. As a result, there will be a penetration of boron ions through the thin gate oxide (on the order of 20-50 .ANG.) which introduces boron ions to the underlying silicon substrate. Boron penetration results unfortunately in degrading the reliability of the devices, such as positive shifts in the threshold voltage, increased sub-threshold swing, and increased electron trapping.
Accordingly, the problem of boron penetration through the thin gate oxide due to scaling-down has become one of the major concerns for advanced CMOS technology. There are known in the art of various techniques which have been used for suppressing boron penetration. One such method is the use of nitrogen implantation into the p.sup.+ poly-Si gate. Another known method in the prior art is utilizing of an amorphous silicon gate. Also, still another known method involves the use of a stacked amorphous silicon/poly-Si gate. However, all of these aforementioned approaches suffer from the disadvantage of increasing the complexity of the conventional CMOS fabrication process. This is because of the different deposition process required for the poly as well as different etching processes needed to remove the poly.
In view of the foregoing, there still exists a method for fabricating advanced CMOS integrated circuits so as to prevent boron penetration through the thin gate oxide of P-channel devices, which require only minimal modification to the conventional CMOS fabrication process.